SPI slave control register
| SPI_CLK_MODE | SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state. |
| SPI_CLK_MODE_13 | {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]. |
| SPI_RSCK_DATA_OUT | It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge |
| SPI_SLV_RDDMA_BITLEN_EN | 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others |
| SPI_SLV_WRDMA_BITLEN_EN | 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others |
| SPI_SLV_RDBUF_BITLEN_EN | 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others |
| SPI_SLV_WRBUF_BITLEN_EN | 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others |
| SPI_SLV_LAST_BYTE_STRB | Represents the effective bit of the last received data byte in SPI slave FD and HD mode. |
| MODE | Set SPI work mode. 1: slave mode 0: master mode. |
| SPI_SOFT_RESET | Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state. |
| SPI_MST_FD_WAIT_DMA_TX_DATA | In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer. |